Arm's Advanced Microcontroller Bus Architecture (AMBA) has a long history of collaborating with the ecosystem to solve complex and industry-wide problems. Now, as the industry embraces chiplets, is the time to extend AMBA from on-chip to multi-chip.
In this blog, we outline AMBA’s approach with Coherent Hub Interface(CHI) Chip to Chip (C2C) – an extension to on-chip CHI that is being developed to make CHI suitable for connecting chip(let)-to-chip(let).
We also illustrate how AMBA CHI C2C will complement chiplet standardization efforts like UCIe, with a view to drive further alignment and collaboration.
As we discussed in a previous blog post, the industry is now at an inflection point where chiplets are being adopted across various segments and applications.
Investment in chiplets is driven by the huge economic pressures currently at play in SoC design. The complexity and performance requirements of SoCs continue to grow, and so does the costs of each new advanced silicon fabrication technology node (5nm and below). However, the benefits of such new nodes are not increasing accordingly. For example, logic continues to scale, but I/O and memory are seeing diminishing returns. The very high costs also hinder the creation of new SoCs or derivatives.
This scenario creates the perfect opportunity for chiplets. Chiplets enable scaling beyond current performance limitations imposed by die sizes, while still managing silicon cost and offering greater composability.
AMBA has been the open standard for on-chip communications. AMBA provides a common standard for various designs, ensuring compatibility between different components in an SoC. It provides flexibility, scalability, design reuse, and low-friction design integration.
AMBA specifications, such as CHI and AXI, are freely available and developed collaboratively with partners from across the industry. AMBA is widely used, by the Arm ecosystem and beyond. It has a long history of dependability and trust, has been shipped in billions of devices, for over 27 years, and across various market segments and applications.
The standardization enabled by AMBA underpins SoC design and the fabless semiconductor model today. This standardization has been the basis of a thriving ecosystem and a comprehensive marketplace of compatible IP and tools. That includes processors, accelerators, interconnects, controllers, and peripherals, as well as verification IP (VIP), modeling tools, performance tools from silicon partners, IP vendors, and other partners.
Standardization is critical to the adoption of chiplets as well. Standardization will be even more important to enable an open ecosystem of chiplets in the future as the industry moves from custom chiplet platforms today onto multi-vendor composable chiplets.
Having a standardization approach with well-defined and interoperable layers is also critical.
Well defined and interoperable layers enable design reuse, reducing cost and time-to-market. Different implementations can prioritize and focus on different use cases and requirements, providing greater flexibility and fostering innovation.
Chiplets will require physical, transport, and protocol layer standardization. Not to mention a software model, standards for mechanical, thermal, and power. And silicon qualification, reliability, compliance testing, and many other elements.
The AMBA CHI architecture provides the performance and scale required for systems with a very large network of processors, accelerators, and memory.
More fundamentally, CHI is high speed, credited, and packetized, which makes it ideal for chiplets as well. At the same time, it is a widely used open standard, which provides a low risk and straightforward adoption path for chiplets.
The CHI protocol provides a full cache coherency model that is architecture neutral, with support for snoop filter and directory-based systems for scaling. It was announced back in 2013 and has been evolving since, with new features and performance improvements being added. Its extensive feature list includes, for example:
CHI has been highly successful as the foundation for infrastructure applications in hyperscalers, servers, and networking. CHI is now broadly adopted and proven in many other applications across multiple market segments, such as in mobile and automotive, where full hardware coherency and high performance are also required.
We are pleased to introduce AMBA CHI C2C, an extension to CHI for connecting chip(let)-to-chip(let).
By C2C, or chip(let)-to-chip(let), we mean both chiplets (i.e. multi-die or die-to-die) and chip-to-chip (i.e. multi-chip through a PCB).
CHI C2C targets advanced heterogeneous systems use cases, as well as Arm-based coherent SMP. It offers a unified interface for device attach, including compute, accelerators, and memory. Not only for fully coherent traffic, but for I/O and non-coherent traffic as well.
CHI C2C focuses on the protocol and packetization layers. CHI C2C leverages the existing on-chip CHI protocol and defines how it is packetized, making it suitable to be transported over a chip(let)-to-chip(let) link. The packetization format optimizes for link utilization and latency, while avoiding complex packing and unpacking schemes.
The same architectural features can extend across chip(let) boundaries and chip(lets) can share the same memory and security models. This ability prevents protocol conversions, incompatibilities, and additional latency.
This layered approach offers a clean separation from the underlying transport, so that CHI can be used on top of UCIe or other options, standardized or not.
UCIe has pulled together industry leaders to provide a standardized die-to-die interface and is seeing great momentum. It provides a physical layer (PHY) and adapter optimized for die-to-die integration, as well as a software model and compliance testing.
UCIe also offers great protocol flexibility. It provides a multi-stack approach, which allows multiple protocols to be used across a single physical link. PCIe and CXL can be used for traditional off-chip devices, and the Streaming interface can be used to plug in other protocols – making it ideal to transport AMBA CHI.
Below we illustrate an example of a multi-die, CHI-based system using UCIe Streaming. It has significant benefits:
The CHI C2C specification is under development and, like all other AMBA specs, will be published following the existing AMBA licensing and governance model. Meaning, it will be freely available, royalty free, architecture neutral, and have broad and perpetual implementation rights[1] -- in other words, ideal for widespread adoption.
By leveraging the existing AMBA licensing and governance model, CHI C2C will be able to evolve in lock-step with the CHI protocol itself; and in alignment with the requirements of the existing AMBA ecosystem. While of course, we ensure it remains optimized for UCIe and other transports.
This model follows the layering approach for standardization and the existing governance model of other protocols, like CXL and PCIe that can also be used in conjunction with UCIe.
With that in place, we expect CHI C2C to be used across various segments and applications. From high-performance infrastructure applications, to automotive and others over time. It is also important to recognize the vast number of existing AXI-based designs, which will be critical to enable in C2C.
We look forward to continuing the collaboration around C2C, and to enabling the industry with the tools to build great standards-based chiplets solutions.
Explore AMBA
[1] For more details, see the AMBA Specification Licence on, for example, page 4 of the AMBA CHI specification document.
What is the exact functoin of this adapter?
Hi, Is there similar work in progress to enable D2D(die to die) with AXI.
Thanks
Tejpal
Coherent masters with CHI or ACE interfaces in heterogeneous chiplets are waiting the standardized bridge protocol to connect with existed link-layer protocol, such as UCIe and CXL. CHI/ACE -> CXS/CPI -> CXL/UCIe data stream might be hopeful.
Hence, would ARM propose these bridge IP in the future and when?
I agree to this concept. I also would like to know the time line of this.
Hello,
Thank you for your interest. Unfortunately, we do not have a precise publication timeline to share at this point. But we will let everyone know once the specification is publicly available.
Regards,
Steve Demski, Arm